Analysis of Advanced Semiconductor Packaging Technology
업데이트 시간: 2022-05-25 17:07:33
The emergence of advanced packaging has opened the industry's eyes to the tremendous potential to drive high-density integration, performance improvement, size miniaturization, and cost reduction of chips through packaging technology. As the pace of IC manufacturing process development along Moore's Law slows, advanced packaging technology is becoming the new engine of IC industry development.
1. Development of integrated circuits and packaging
The chip consists of a Die and peripheral package structure, which determine the chip's performance. The International Technology Roadmap for Semiconductors ITRS states that integrated circuit technology will develop in two directions: More Moore and More than Moore. The More Moore's Law technology path focuses on reducing transistor size and increasing IC density. In contrast, the More Moore's Law technology path focuses on using packaging technology to improve chip and system integration.
As advanced processes approach atomic size, the short-channel effect and quantum tunneling effect make transistors exponentially more challenging to manufacture. And, as the process improves, the overall cost will increase dramatically. 5nm chip design costs are already eight times higher than 28nm chips, which is unaffordable for most companies. Throughout the world, only TSMC, Samsung, and Intel have a 7nm process and strength to 3nm, 2nm development. Therefore, through the packaging technology to reduce costs, the system miniaturization and multi-functionalization have become the new engine power of the chip industry development.
2. Semiconductor packaging technology
Packaging is the method, structure, and process of encapsulating integrated circuit chips in a standard component, with the role of protection, fixation, sealing, and enhancing the electrical and thermal properties of the chip as the bridge between the chip and the system, the chip after packaging can be installed on the PCB as a standard component to achieve the application.
With the development of the semiconductor process, the number of chip pins gradually increases, and the package form also develops from a standard package (lead frame as a carrier, using lead bonding interconnection) to an advanced package. In single-chip packages, advanced packages improve the integration density and electrical interconnection speed of chips, lower the design threshold, and optimize the flexibility of function matching compared to standard packages. With the diversification and combination of package forms, advanced packages refer to single-chip packages and include the system in a package (SiP), which integrates at least two chips.
3. advanced packaging technology analysis
At present, the representative technologies of advanced packaging include Flip Chip, Through Silicon Via (TSV), Wafer-level Packaging (WLP), and System in Package (SiP) technologies.
A flip chip is a chip connected directly to the interface on the package substrate through a bump.
Compared to traditional lead bonding packages, the flip-chip has main advantages.
Performance, it can reduce the parasitic capacitance brought by the leads, which is conducive to increasing frequency and improving electrical and thermal performance.
Economic aspect, simple process, and lower cost.
Space, reduce the package volume so that the finished package and the chip size are comparable, to achieve Chip-Size Packaging;
Through Silicon Via (TSV)
TSV technology is mainly used in three-dimensional packages to provide electrical extension and interconnection for the chip in the vertical direction. Depending on the type of integration, TSV is divided into 2.5D and 3D, with the 2.5D vias located at the intermediate layer and the 3D vias running through the chip itself, directly connecting the upper and lower layers of the chip.
The 3D TSV technology enables direct connection of the upper and lower chips with the same structure, thus enabling large bandwidth and low latency data transfer. This feature is extremely well matched to the needs of memory chips, increases the transfer speed between memory chips, reduces power consumption, and has been heavily used in high-end Flash and DRAM stacks.
2.5D TSV technology can provide ample bandwidth and low latency data transfer for multiple chips in the same package and has been used in CPUs and GPCs in combination with 3D TSV packaging.
Wafer Level Packaging (WLP)
The traditional packaging process is to cut wafers into Die before packaging, while wafer-level packaging is packaged before cutting. Wafer level packaging can significantly reduce the size of the chip after packaging, can also improve the speed and stability of data transmission, and is widely used in consumer electronics chips.
RDL (Redistribution Layer), as the core technology in wafer-level packaging, plays the role of XY plane electrical extension and interconnection. IO ports are generally distributed on the edges or around the chip in chip design and manufacturing. In order to facilitate connection with the outside world, metal layers and corresponding dielectric layers need to be deposited on the wafer surface, and metal wiring needs to be formed to rearrange the IO ports to a loosely located area and form a face array arrangement.
System in Package (SiP)
SiP forms a system or subsystem from multiple active electronic components (usually bare chips), passive devices, and other devices (MEMS or optical devices, etc.) with different functions. It assembles the multiple systems inside a package body to make it a single package part with specific functions. In terms of connection methods, flip-chip (FC), rewiring (RDL), and embedded (Embedded Die) are the three common technical routes to achieve SiP.
Chiplet technology is a widely studied SiP technology that breaks down each functional area of a single chip into multiple independent chips and reconstitutes a complete system through packaging technology. Compared with the traditional single chip, the single chip area with Chiplet technology is more petite, improving the manufacturing yield and achieving heterogeneous integration.
4. Application examples of advanced packaging
The semiconductor industry has achieved a fine division of labor, and the industry chain is mainly composed of design, production, packaging, and testing. Advanced packaging promotes the interpenetration and integration of front and back channel processes, and manufacturers with high technical barriers and technology accumulation will extend to upstream and downstream processes. Nowadays, the head manufacturers have become the main force in the advanced packaging industry with their respective advantages, mainly Intel, Samsung, and TSMC.
In 2017, Intel launched the EMIB (Embedded Multi-die Interconnect Bridge), an important step in advancing advanced packaging. The packaging technology can package CPU, IO, GPU, and even FPGA, AI, and other chips together. It can package chips of 10nm, 14nm, 22nm, and other different processes together into a single chip to adapt to flexible business needs. 2019, Intel launched Foveros technology, which began to stack chips vertically for horizontal and vertical interconnections, achieving 3D stacking. Immediately afterward, at SEMICON West 2019, Intel combined EMIB with Foveros technology.
The semiconductor field is currently in a new stage of rapid development. Advanced packaging is the key path for system integration and functional convergence in the post-Moore era, which will become a new competitive market for chip manufacturing and packaging companies.
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