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> Embedded technology > Chip Embedded Technology Enables High Current Density Power

Chip Embedded Technology Enables High Current Density Power

업데이트 시간: 2021-05-18 10:54:27

This paper highlights TDK 3D design technologies that can help reduce parasitic losses and improve thermal performance, while also reducing PCB footprint. 


Over the past 10 years, DC-DC power modules have evolved to feature emerging chip-embedded technologies with the latest enhancements in thermal packaging that allow for higher density module designs in smaller form factors. Today's power modules include: 1) DC-DC converters that include FETs and drivers; 2) integrated inductors; 3) passive devices for Vcc and startup activation; and 4) in some cases, communication for advanced power functions.


3D design techniques can help reduce parasitic losses and improve thermal performance, while also reducing the PCB footprint. These key factors benefit DC-DC applications that require compact design, highest current density and power output.


New Technologies

The paradigm shift required for miniature point-of-load power (μPOL™) modules in the near future requires advanced technologies and a cross-functional approach.

  1. Package designs that address heat dissipation and regulation performance

  2. Innovative integrated circuit (IC) designs that enable high-precision compact regulator designs

  3. Parallel magnetic and discrete component development

  4. Three-dimensional design methods for all on-package components

  5. Manufacturing technology developments to achieve sustainability and reliability

Chip Embedded Technology Enables High Current Density Power.jpg

                                                                                                               Figure 1: Chip Embedded Power Module Technology

The figure above shows an example of the latest developments in chip embedded power module technology. The IC containing the DC-DC regulator circuitry is embedded in a thermally enhanced packaging technology called semiconductor embedded substrate (SESUB). The embedded IC chip and SESUB technology includes a patented implementation of a copper heat sink layer and a 3-dimensional structure of metal and laminate materials, which reduces the thermal resistance path to the bottom side of the package substrate. Module substrates with embedded cores have a maximum thickness of 300 μm. SESUB technology eliminates the need for lead bonding, thereby greatly reducing unnecessary parasitic losses while increasing the strength of the mechanical package. Historically, lead bonds have been prone to breakage during severe vibration and drop tests.


The top mounting surface of the thin substrate is then filled with industry leading thin film power inductors, resulting in a total thickness of 1.5 mm high. With a thickness of just 1.5 mm, this technology opens the door to thin DC-DC solutions that enable PCB board layouts that bring the power supply closer to the load. This is key for upcoming 7 nm ASICs, SoCs, FPGAs and multi-core ARMs with sub-3 nm highly constrained heatsink coverage.


Example of a 3D chip embedded power module

The figure below shows the complete high-density power module, offering 15W (FS1406) and 30W (FS1412) with heights of 3.3mm x 3.3mm x 1.5mm for 6A and 4.9mm x 5.8mm x 1.6mm for 12A, respectively. 6A devices offer 650 A current density per cubic inch, while 12A devices offer over 1000 A per 6A devices provide 650 A current density per cubic inch, while 12A devices provide over 1000 A current density per cubic inch, both two to four times higher than current DC-DC power module technology. These numbers will increase in the near future with the development of 25 A to 200 A current sharing modules and 3 mm to 4 mm height profiles. These will be well suited for the high current density core voltages in upcoming artificial intelligence (AI) SoCs and ASICs for small applications.

Chip Embedded Technology Enables High Current Density Power-2.jpg

                                                                                         Figure 2: 3D Chip Embedded Power Module (TDK's addition)

Chip Embedded Technology Enables High Current Density Power-3.jpg

                                                                                        Figure 3: Thermal performance 3D chip embedded power module

Chip Embedded Technology Enables High Current Density Power4.jpg

                                                                              Figure 4A: Practical design for high density using 3D chip embedded power modules


Breaking the performance barrier

The new 3D technology features a highly sustainable production yield and excellent thermal performance in a bare and packaged top package, which reduces the need for output current reduction in higher temperature ambient conditions. While smaller, older power module technology solutions typically reduce output current by 40% when ambient temperatures approach 60°C to 90°C, this is rarely the case with the new μPOL3D technology power modules. Figure 3 shows the thermal performance from 3A to 12A at different output voltages and ambient temperatures in the absence of airflow convection. The thermal path from the hottest part of the core to the heat sink of the SESUB packaging method proves the functionality of TDKμPOL™3D chip embedded technology.


These data confirm that the technology enables a staggering 1 watt per cubic millimeter current density!


The FS1406, 6A power module translates to real world applications, delivering full rated current of 80°C at 12V input to 1V output, with little output current derating at zero airflow (operating range -40°C to + 125 C) providing margins for higher ambient board temperatures. This can help reduce the space and weight of cooling costs in industrial and communications applications.


Putting them together for practical applications.

Figure 4A shows the results of a system-on-module (SoM) design using a Xilinx Zynq 7 with a 3μPOL3D power module. The entire DC-DC solution has a power output of 6 W to 10 W. Each module and off-module output capacitor has an area of 49 mm2 next to the FPGA. The simplicity of the power module requires minimal output load capacitors, eliminating the need for traditional compensation components and additional voltage divider resistors, which further reduces space and cost. The use of 0.5 to 2 oz copper PCB thermal vias and the correct board layout provide excellent thermal performance with only + 13°C temperature rise (no airflow) between three power modules separated by 6 mm. The embedded approach reduces the size of the SoM card to 43.7 mm x 17.8 mm, reducing board space by up to 30 percent compared to similar solutions.

Chip Embedded Technology Enables High Current Density Power5.jpg

                                                                                                 Figure 4B: Typical PCB Design Footprint - Overall Solution

The table in Figure 4B shows typical design dimensions using these high current density power modules to calculate board spacing benefits. They are ideal for placing DC-DC power solutions between FPGAs, ASICs, memories and in the surrounding nooks, crannies and voids. Under heat sink covers and/or on the top or bottom of motherboards and daughter cards to increase design flexibility. Power supply summary: FS1406 provides 6A (15W) power in 49 mm2; FS1412 is 12A (30W) in 105 mm 2.


Industrial testing and performance reliability

3D chip embedded technology and the ability to produce sustainable long-term availability is now available in high volume. Expanded reliability testing includes 1) JESD22-A108 for high temperature (up to 125°C) with no failures, 2) JESD22-A104 for failure-free 3000 power cycle testing, and 3) mechanical vibration and shock testing. For more information on EMI performance (e.g. CISPR-11 performance).


Conclusion

The next generation of new technology power modules is already in development and available on the market. The advantages of the chip-embedded 3D power module or TDK's μPOL™ are

  1. Higher current/power density

  2. Smaller size solutions for today's power supply challenges

  3. Thin (height) packaging to address emerging trends in system design

  4. Improved thermal performance

  5. More robust packaging solutions


These factors will open new doors for overall higher PCB board density and size reduction, power transfer line loss reduction, and weight reduction of the entire power supply plus thermal solution.


공유:

이전: PAMISS: Intel's Six Technology Pillars-Memory

다음: ST is considering the acquisition of Nordic

 

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